Reza Baharani

Scientific Researcher

Developing a self-supervised training framework tailored for transformer-based architectures in the realm of computer vision, with a focus on enhancing contextual understanding in 2/3-D pose estimation tasks.

Developed a discrete Variational Auto-Encoder (dVAE) to accurately capture the dynamics of pose movement over time in a discrete latent space, enabling effective classification of pose movements.
Training transformer-based models, including those based on ViT and BERT-like architectures, through generative and contrastive self-supervised approaches. This involves masked input frame generation and frame sequence verification.

Engaging in MLIR (Multi-Level Intermediate Representation) projects to lower machine learning models for custom hardware designed on FPGA as a potential target platform.

Examining and evaluating open-source initiatives like CIRCT alongside pre-existing MLIR batteries, such as torch/tensorflow-mlir.

Lead Edge/IoT Deep Learning Engineer

Led a smartphone software development team in leveraging AI and 3D pose estimation to assess and minimize fall risk and cognitive impairment in older adults, achieving performance up to 20 FPS on the device SoC. Demo

• Large scale parallel training and validation of a novel human 3D pose estimation algorithms on datasets such as Human3.6M and NTU-RGB+D (2.3 TB)
• Developed Swift code to integrate TensorFlow TFLite and Apple MLPackage models with CoreML for NE(NPU)/CPU/GPU processing and utilized React Native to establish the connection between AI and user interface.
• Leveraged ASW cloud services such as Cognito, DynamoDB, and S3.

MLOps Engineer

Designed and implemented an end-to-end scalable, intelligent advanced video surveillance vision pipeline, achieving a system performance of 23 frames per second (FPS) for eight concurrent cameras at Full HD resolution. Demo.

Utilized four deep learning models for the purposes of detection, re-identification, body pose estimation, and segmentation.
Trained a person re-ID model on large datasets, including DukeMTC, CUHK03, and Market1501, enhancing its accuracy for mixed-precision inference.
Used PyTorch Multiprocessing Process and Queues to parallelize models inference.
Leveraged the Flask module to construct a RESTful API that serves an ML model for re-identifying individuals across different camera clients.

Graduate Student Research Assistant

Designed and developed Agile Temporal Convolutional Neural Network (ATCN), a scalable deep learning model with adjustable hyper-parameters to enable time series analysis for resource-constrained edge systems.

Implemented in C/C++, the solution consumed only 49% of the 320KB RAM and 15% of the 1MB flash memory available on a Cortex-M7 microcontroller.
Used data augmentation techniques, such as jittering, magnitude warping, window warping, and scaling, to enhance model robustness on the UCR 2018 dataset.

Invented a customized multi-head attention Temporal Convolutions Network (TCN) for efficiently and precisely predicting highway vehicle trajectories for highway and self-driving cars safety applications.

Redesigned dilated TCN with separable depth-wise convolutional neural network to reduce the model size and complexity by approximately 33.16% compared to LSTM-based approaches.

Implemented HW/CW co-design for application-specific architectures, accelerating EfficientNet and MobileNetV2 inference on Xilinx embedded and cloud FPGAs. Achieved an improvement of up to 8.6x FPS/W. Demo

Architectural model optimization such as quantization (4-bit), layers fusion, pruning, and activation approximation.
Hardware level optimization includes pipelining, window buffering, etc.

Designed a recurrent deep learning solution for real-time edge processing in reliability modeling of Si-MOSFET power electronics converters.

Designed stacked LSTM networks for time series analysis.
Utilized a NASA dataset for training and validation, enhancing the accuracy and efficiency of the system.

Experienced in administration, system driver configuration, and resource allocation, including hardware RAID setup for multiple servers with server-class GPUs such as P100, V100, RTX 6000. Skilled in configuring deep learning frameworks like TensorFlow and PyTorch to optimize performance across various server

University of North Carolina at Charlotte